//FileName   : jtag
//Author     : -
//Description: jtag
//ModifyDate : 2019-4-15
//Company    : -
//Copy right : -


module jtag (
    input               tck,
    input               trst,
    input               tms
);

//internal temp define
reg           test_logic_reset;
reg           run_test_idle;
reg           select_dr_scan;
reg           select_ir_scan;
reg           capture_dr;
reg           exit1_dr;
reg           shift_dr;
reg           update_dr;
reg           pause_dr;
reg           exit2_dr;
reg           capture_ir;
reg           exit1_ir;
reg           shift_ir;
reg           update_ir;
reg           pause_ir;
reg           exit2_ir;



//---------------------------------------------
//Function: AA
//---------------------------------------------

always @(posedge tck or negedge trst)
begin
    if(!trst)
        test_logic_reset <= 1'd0;
    else begin
    if( select_ir_scan )
    begin
        if( tms )
            test_logic_reset <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        run_test_idle <= 1'd0;
    else begin
    if( test_logic_reset )
    begin
        if( !tms )
            run_test_idle <= 1'b1;
    end
    else if( update_dr )
    begin
        if( !tms )
            run_test_idle <= 1'b1;
    end
    else if( update_ir )
    begin
        if( !tms )
            run_test_idle <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        select_dr_scan <= 1'd0;
    else begin
    if( run_test_idle )
    begin
        if( tms )
            select_dr_scan <= 1'b1;
    end
    else if( update_dr )
    begin
        if( tms )
            select_dr_scan <= 1'b1;
    end
    else if( update_ir )
    begin
        if( tms )
            select_dr_scan <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        select_ir_scan <= 1'd0;
    else begin
    if( select_dr_scan )
    begin
        if( tms )
            select_ir_scan <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        capture_dr <= 1'd0;
    else begin
    if( select_dr_scan )
    begin
        if( !tms )
            capture_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        exit1_dr <= 1'd0;
    else begin
    if( capture_dr )
    begin
        if( tms )
            exit1_dr <= 1'b1;
    end
    else if( shift_dr )
    begin
        if( tms )
            exit1_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        shift_dr <= 1'd0;
    else begin
    if( capture_dr )
    begin
        if( !tms )
            shift_dr <= 1'b1;
    end
    else if( exit2_dr )
    begin
        if( !tms )
            shift_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        update_dr <= 1'd0;
    else begin
    if( exit1_dr )
    begin
        if( tms )
            update_dr <= 1'b1;
    end
    else if( exit2_dr )
    begin
        if( tms )
            update_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        pause_dr <= 1'd0;
    else begin
    if( exit1_dr )
    begin
        if( !tms )
            pause_dr <= 1'b1;
    end
    else if( pause_ir )
    begin
        if( !tms )
            pause_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        exit2_dr <= 1'd0;
    else begin
    if( pause_dr )
    begin
        if( tms )
            exit2_dr <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        capture_ir <= 1'd0;
    else begin
    if( select_ir_scan )
    begin
        if( !tms )
            capture_ir <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        exit1_ir <= 1'd0;
    else begin
    if( capture_ir )
    begin
        if( tms )
            exit1_ir <= 1'b1;
    end
    else if( shift_ir )
    begin
        if( tms )
            exit1_ir <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        shift_ir <= 1'd0;
    else begin
    if( capture_ir )
    begin
        if( !tms )
            shift_ir <= 1'b1;
    end
    else if( exit2_ir )
    begin
        if( !tms )
            shift_ir <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        update_ir <= 1'd0;
    else begin
    if( exit1_ir )
    begin
        if( tms )
            update_ir <= 1'b1;
    end
    else if( exit2_ir )
    begin
        if( tms )
            update_ir <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        pause_ir <= 1'd0;
    else begin
    if( exit1_ir )
    begin
        if( !tms )
            pause_ir <= 1'b1;
    end
    end
end

always @(posedge tck or negedge trst)
begin
    if(!trst)
        exit2_ir <= 1'd0;
    else begin
    if( pause_ir )
    begin
        if( tms )
            exit2_ir <= 1'b1;
    end
    end
end

endmodule
